In recent years, it is demanded to improve reliability of a semiconductor integrated circuit used in various fields. Particularly high reliability is demanded in a semiconductor integrated circuit used for a product which affects human life resulting from a failure, as in a driver circuit for a liquid crystal monitor used in a car navigation system and in a medical field. For the purpose of such high product reliability, one of schemes to be required is to strong endurance to an overvoltage (or ESD) applied from the outside. That is, an integrated circuit with high ESD endurance is demanded.
In order to enhance ESD endurance in an LSI (Large Scale Integration), a protection element against ESD (i.e. ESD protection element) is generally provided between an internal circuit of an LSI and input/output pad. The ESD protection element prevents the internal circuit of LSI from being destroyed by changing a path for a surge current generated by ESD.
Generally, an MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), a bipolar transistor and a thyristor are used as the ESD protection elements. For example, the ESD protection element using an NPN bipolar transistor is disclosed in “ESD Protection Considerations in Advanced High-Voltage Technologies for Automotive”, and IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, No. 8, AUGUST 2005 P. 1751.
Referring to FIGS. 1 to 3, a conventional ESD protection element using a bipolar transistor will be described. FIG. 1 is a cross sectional view showing a sectional structure of the conventional ESD protection element along A-A′ shown in FIG. 2. FIG. 2 is a plan view showing a structure of the conventional ESD protection element. FIG. 3 shows an equivalent circuit of the conventional ESD protection circuit.
Referring to FIG. 1, in the conventional ESD protection element, and an N− embedded layer (NBL) 102 is formed on a P-type substrate (P-sub) 101 in a Z-axis direction, and an N− collector region 103 and an N+ lead-out region 105 are formed on the N− embedded layer (NBL) 102. A P− base region 104 is formed on the N− collector region 103 to function as a base region. a high-concentration P+ diffusion layer 87 (to be referred to as P+ base diffusion layer 87, hereinafter) and a contact 84 which function as a base electrode B20 and a high-concentration N+ diffusion layer 88 (to be referred to as N+ emitter diffusion layer 88 hereinafter) and a contact 85 which function as an emitter electrode E10 are provided on the P− base region 104. Also, a high-concentration N+ diffusion layer 89 (to be referred to as N+ collector diffusion layer 89) and a contact 86 which function as a collector electrode C10 are provided on the N+ lead-out region 105. The P+ base diffusion layer 87, the N+ emitter diffusion layer 88 and the N+ collector diffusion layer 89 are separated from each other by an element separation region 106.
Referring to FIG. 2, the P+ base diffusion layer 87 is connected to a grounded metal wiring 81 via a plurality of the contacts 84 arranged in a direction of a base width W (or in a Y-axis direction). The N+ emitter diffusion layer 88 is connected to the grounded metal wiring 81 via a plurality of the contacts 85 arranged in the base width W direction (or in the Y-axis direction). Similarly, the N+ collector diffusion layer 89 is connected to a pad via a plurality of the contacts 86 arranged in the direction base width W (or in the Y-axis direction) and a metal wiring 82. The pad is connected to an internal circuit (not shown).
Referring to FIGS. 1 to 3, a region of the P− well 104 which is straightly below the N+ emitter diffusion layer 88 is referred to as a base region B10. When a high voltage is applied to the pad due to ESD, a breakdown occurs in a junction between the base region B10 and the collector terminal C10, and holes generated in the vicinity of the junction flow into the base terminal B20 and electrons generated in the vicinity of the junction flow into the collector electrode C10. At this time, a voltage in the base region B10 (i.e. base voltage) increases based on a voltage drop generated by a parasitic resistance RB between the base region B10 and the base electrode B20. A diode between the emitter electrode E10 and the base region B10 is turned on through increase of the base voltage and a surge current due to ESD starts flowing between the collector electrode C10 and the emitter electrode E10. Thus, it is possible to prevent the surge current due to ESD from flowing into the internal circuit.
When the ESD surge current flows from the collector electrode C10 to the emitter electrode E10 in the bipolar transistor, heat is generated with an electric field which is present in a depletion layer generated in a junction breakdown region (i.e. in the vicinity of a junction region between the collector and the base or in the vicinity of a boundary between the embedded collector layer and the base) and a current due to flow of electrons from the emitter electrode E10 to the depletion layer. Meanwhile, since the plurality of the contacts 85 and 86 are arranged in the base width W direction (or in the Y-axis direction shown in FIG. 2), a plurality of current paths are present between the collector and the emitter. A current amount is not uniform between the plurality of current paths but varies in the base width W direction (or in the Y-axis direction). That is, a region in which a large surge current flows and a region in which a small surge current flows appear between the collector and the emitter. The region with the large current amount is accompanied by a high temperature, compared with the region with the small current amount, and as a result of this, carriers increase to reduce a resistance of the region, resulting in a further larger current to flow. For example, referring to FIG. 2, a larger amount of surge current flows in a region with a current amount and temperature locally increased more than other regions. If a current is concentrated locally in this way, element destruction is easy to occur in the region, which leads reduction of ESD endurance in an ESD protection element as a whole.
In addition, U.S. patent (U.S. Pat. No. 6,587,320 B1) is known as a prior art.
As described above, in the conventional ESD protection element, element destruction occurs because of current concentration (or thermal runaway) due to deviation in a current density in the base width W direction (or in the Y-axis direction), whereby ESD endurance is reduced.